1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a thin film transistor liquid crystal display device having a high aperture ratio.
2. Discussion of the Related Art
An aperture ratio of a liquid crystal display device is a ratio of an area which a light penetrates with respect to an entire area of the pixel. Such a ratio is important for picture quality of the device.
One of the methods for increasing the aperture ratio is shown in FIG. 1, where a pixel electrode is enlarged over data lines and a black matrix is not necessary between the data lines and the pixel electrode.
FIG. 1 is a plan view of a pixel module 100 of a conventional liquid crystal display device. The module 100 is defined by gate lines 2 and 3 adapted for carrying gate drive signals to the pixel modules and data lines 16 and 18 adapted for delivering data signals to the pixel modules. The gate line 3 has a gate electrode 4, the data line 16 has a source electrode 6, and a pixel electrode 12 is connected to a drain electrode 8 of a thin film transistor (TFT) denoted by "T" through a contact hole 10. A storage capacitor for the device is denoted by "S".
As shown in FIG. 1, in order to increase the aperture ratio, the pixel electrode 12 overlaps the data lines 16 and 18, and there is no interval or space between the data lines and the pixel electrode 12. Thus, no opaque mask or black matrix for blocking side edges of the pixel module 100 is needed, which increases the aperture ratio of the LCD.
However, there is still an interval "L" between the gate line 3 and the pixel electrode 12, as shown in FIG. 2 which is a cross sectional view taken along the line II--II of FIG. 1. Thus, a black matrix (light shielding layer) for blocking the interval "L" is needed, which decreases the aperture ratio.
Overlapping the gate line 3 with the pixel electrode 12 in order to cover the interval "L", as shown in FIG. 3, causes increased parasitic capacitance (designated by the area "OL") between the pixel electrode 12 and gate line 3. Such parasitic capacitance may cause flicker.
FIG. 4 is a corresponding schematic circuit diagram of FIG. 3. The parasitic capacitance C.sub.gp,i between the overlapped portion of the pixel electrode 12 and the gate line 3 is connected to the liquid crystal capacitance C.sub.LC,i. Thus, during the off-time of the TFT "T", the liquid crystal layer is influenced by the parasitic capacitance C.sub.gp,i which deteriorates the picture quality.
In FIG. 4, the symbols V.sub.g,i and V.sub.D,i designate voltages for the gate electrode and the data line, respectively.